This invention is in the field of computers, and is more specifically directed to bus interface circuitry in microprocessor-based computers such as personal computers and workstations.
As well understood by those in the art, many various bus configurations and protocols are now used, in modern personal computers, portable personal computers, and workstations, for communicating data among the central processing unit (host CPU) and peripheral devices such as memory, disk storage, input/output devices, and, in a multiprocessor system, other CPUs. These multiple bus configurations have resulted from the competing desires of maintaining compatibility of the computer system with older-generation peripheral cards (implemented according to the ISA, EISA, and other older parallel bus standards, such buses generically referred to herein as "legacy" buses), and of providing the performance capability of newer-generation buses, such as the well-known Peripheral Controller Interface (PCI) bus as described in the PCI Local Bus Specification R2.1 from the PCI SIG (Special Interest Group). The special requirements of peripheral devices for portable computers have spawned the development and implementation of even more bus protocols, including the well-known PCMCIA bus, and a 32-bit variant thereof referred to in the art as the "CardBus" bus (CardBus being a trademark of the Personal Computer Memory Card International Association).
Conventional computer systems typically include interface "chipsets", typically installed in the computer system on the same main circuit board (i.e., "mother board"). These interface chipsets include multiple integrated circuits for interfacing the external bus of the host CPU (typically referred to as the "host bus"), with the various peripheral and system devices. FIG. 1 illustrates a conventional microprocessor-based computer system 200, as an exemplary arrangement of a host CPU 210, the interface chipset CS, and the various buses that are used in connection with conventional computers. System 200 of FIG. 1 is presented herein by way of example and for description purposes only, it being understood that conventional systems may be constructed with more or fewer resources than shown in FIG. 1, and in various differing arrangements.
Host CPU 210 in system 200 of FIG. 1 is a conventional microprocessor as currently used in modern, high-performance, personal computers, workstations, and portable computers; for example, host CPU 210 may be an x86-architecture microprocessor of the so-called P5 or P6 class (corresponding, for example, to the PENTIUM and PENTIUM PRO microprocessors available from Intel Corporation). Host CPU 210 communicates with the other elements of system 200 primarily by way of host bus 212; host bus 212 operates according to the particular external bus protocol driven by host CPU 210, as known in the art. Typically, host bus 212 is a lightly-loaded bus, implemented with a "back-plane" of minimum length to minimize bus loading and losses and thus to maintain high speed data transfer.
Chipset CS in system 200 of FIG. 1 includes several separate integrated circuits, typically mounted on the mother board of system 200 along with host CPU 210, each providing an interface between host bus 212 and a system resource. In this example, chipset CS includes cache controller 214, which controls communication of data between host CPU 210 and external cache memory 216, typically implemented as high-speed static RAM, and serving as a level-2 or level-3 cache memory depending upon the internal architecture of host CPU 210. Chipset CS further includes main memory controller 218, which controls communication of data between host CPU 210 and main memory 220, which is typically implemented as banks of dynamic RAM.
Chipset CS in system 200 further includes host/PCI bridge 222, which provides an interface between host bus 212 and a first-level PCI bus 224. PCI bus 224, as is known in the art, is a high-speed, synchronous, bus-mastered-architecture, system bus for providing high-speed data communications among system resources. PCI resources 225a, 225b are illustrated as resident on first-level PCI bus 224, and represent such system resources as high-performance graphics display systems, additional expansion memory, disk storage systems, and other CPUs, in multiprocessor systems. In modern systems, PCI buses are 32-bit buses, operating at either 33 MHz or 66 MHz frequencies using address and data multiplexing, with the capability of 64-bit data transfer provided by an additional level of multiplexing. Current PCI protocols also permit the use of either 5 volt or 3.3 volt logic levels in the 33 MHz mode; only the 3.3 volt level is permissible in 66 MHz operation. Host/PCI bridge 222 is a conventional device known in the art for interfacing PCI bus 224 to host bus 222. In this capacity, host/PCI bridge 222 is necessarily responsible for reformatting the commands, address, and data signals communicated from one bus to another; modern implementations of host/PCI bridge 222 also contain logic to combine commands and to prefetch data, for improved system performance.
Additional levels of buses are provided in system 200 in a hierarchical manner, thus providing system 200 with the ability to use resources of different bus types, and also to reduce the loading on the higher speed buses nearer host CPU 210. In this example, system 200 includes PCI/ISA bridge 226 which is connected between first-level PCI bus 224 and ISA bus 228. ISA bus 228 has ISA resources 230a, 230b resident thereupon, such resources referred to as "legacy" resources (and ISA bus 228 as a "legacy" bus), indicating the older bus protocol with which they operate. PCI/ISA bridge 226, as known in the art, is a resource that reformats signals when communicated from bus-to-bus, and which may also include logic for combining commands and prefetching data.
System 200 also includes PCI/PCI bridge 232 which interfaces first-level PCI bus 224 to two second-level PCI buses 234a, 234b, upon which PCI resources 236a, 236b are respectively resident. PCI/PCI bridge 232 is a known device in the art that is often referred to as a PCI "splitter", as it provides, in this example, interface control between multiple lower-level PCI buses 234 and higher-level PCI bus 224. PCI/PCI bridge 232 thus enlarges the number of potential PCI resources available in system 200 without unduly loading first-level PCI bus 223, and also permits PCI buses 224, 234a, 234b to operate according to different clock speeds, data widths, and logic levels, such options available under the PCI specification.
By way of further background, system 200 in this example also includes PCI/CardBus bridge 240, for interfacing first level PCI bus 224 to CardBus resources 242a, 242b resident on separate CardBus buses 241a, 241b, respectively. As noted above, CardBus buses are variants of the PCMCIA buses, and are particularly suitable for use in portable computers to implement peripherals such as disk drives, modems, and the like. PCI/CardBus bridge 240 is also a known device in the art, such as the PCI1130 CardBus controller available from Texas Instruments Incorporated, which interfaces PCI bus 224 to resources of either the CardBus or PCMCIA type, at either 3.3 volt or 5 volt logic levels.
By providing a standard for high-speed, master-driven, bus architecture, the PCI bus standard is intended to reduce the number of local bus protocols that may otherwise be generated in the marketplace. However, as illustrated in FIG. 1, many different bus types are still utilized in modern personal computers, workstations, and portable computers, even within individual systems. Further, as noted above, the PCI bus itself has several options, including different bit widths, different bus clock rates, and different logic level standards. Accordingly, the size, speed, and protocol of expansion buses continue to proliferate in the field.
It is desirable, from a system cost standpoint, to integrate as many system functions as possible into a single integrated circuit, either of the single-chip type or of the multi-chip module type (i.e., multiple integrated circuit chips assembled into a single integrated circuit package). However, the proliferation of different bus protocols and standards has heretofore rendered integration of the bus interface functions difficult according to conventional techniques, which necessitate the manufacture of host CPUs with different bus interface functions.
By way of further background, one type of configurable bus controller component has been implemented in SparcStation 10 and SparcStation 20 workstations sold by Sun Microsystems, Inc. This bus controller, referred to a MultiCache Controller and manufactured by Texas Instruments Incorporated under the part number TMS390Z55, is configurable in that it is selectably configured to interface a host CPU with one or the other of two mutually exclusive bus protocols.